Department of Electrical and Electronic Engineering

EIE2105 Digital and Computer Systems

Tutorial 4: Sequential Logic I

Q1.  What is the difference between synchronous counter and ripple counter?

Q2.  What is the problem of S-R latch? How can D latch solve this problem?

Q3.  What is the latch timing problem? Explain using an example and a wave/timing diagram.

Q4.  Complete the following timing diagram if the positive-edge triggered T flip-flop is simulated. You can assume gate delays are zero.

Q5.   a.    Which of the following circuits is/are master-slave/edge-triggered flip-flop?

b.     Complete the following timing diagram if circuit A is simulated. You can assume gate delays are zero.

c.     Complete the following wave/timing diagram if circuit B is simulated. You can assume gate delays are zero.

d.     As compared with master-slave S-R flip-flops, what is the advantage of edge triggered D flip-flops on how its output reacts to the input?